Retargetable Functional Simulator Using High Level Processor Models

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - Retargetable Functional Simulator Using High Level Processor Models

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	Similar Articles Articles by Subhash Chandra Articles by Rajat Moona

13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Subhash Chandra, Rajat Moona, "Retargetable Functional Simulator Using High Level Processor Models," VLSI Design, International Conference on, pp. 424, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812644, author = {Subhash Chandra and Rajat Moona}, title = {Retargetable Functional Simulator Using High Level Processor Models}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {424}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812644}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Retargetable Functional Simulator Using High Level Processor Models SN - 1063-9667 SP EP A1 - Subhash Chandra, A1 - Rajat Moona, PY - 2000 VL - 0 JA - VLSI Design, International Conference on ER -

Subhash Chandra, Indian Institute of Technology

Rajat Moona, Indian Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812644

The current embedded systems design typically also involves the design of application specific integrated processors. In such scenarios, the designer needs to study various designs for choosing the best suited one with respect to the performance and the cost. The use of high level processor models along with automated tools is becoming popular in the performance study of the designs.This work involves the design and implementation of a Retargetable Functional Simulator Generator which is capable of generating a functional simulator for a processor given its high level model in the Sim-nML [6] language and a binary for the processor in ELF [1] format. The functional simulator so generated simulates the binary program for the described processor on any other host. It can also produce an uncompressed instruction trace for the binary program.

Citation:

Subhash Chandra, Rajat Moona, "Retargetable Functional Simulator Using High Level Processor Models," vlsid, pp.424, 13th International Conference on VLSI Design, 2000

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