13th International Conference on VLSI Design A Versatile BIST Technique Combining Test Registers and Accumulators Calcutta, India January 04-January 07 ISBN: 0-7695-0487-6
In recent years, many BIST tools have been developed which insert test registers into a circuit at register-transfer level. However, these tools do not exploit all potentialities in test register placement and cause more test overhead than necessary. In this paper, we present a versatile BIST technique which overcomes most restrictions of conventional tools. In addition, instead of using only test registers we also allow for accumulators, which have been proven to be a coequal alternative to test registers but with virtually no hardware overhead. The described approach leads to a BIST implementation with minimized hardware overhead and test application time. Various experimental results show considerable savings in test overhead.
Index Terms:
accumulator, built-in self-test, register-transfer level, test register
Citation:
Frank Mayer, Albrecht P. Stroele, "A Versatile BIST Technique Combining Test Registers and Accumulators," vlsid, pp.412, 13th International Conference on VLSI Design, 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||