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13th International Conference on VLSI Design
Testing Flash Memories
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
ASCII Text
x 
 
Mohammad Gh. Mohammad, Kewal K. Saluja, Alex Yap, "Testing Flash Memories," VLSI Design, International Conference on, pp. 406, 13th International Conference on VLSI Design, 2000.
 
 
BibTex
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@article{ 10.1109/ICVD.2000.812641,
author = {Mohammad Gh. Mohammad and Kewal K. Saluja and Alex Yap},
title = {Testing Flash Memories},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2000},
issn = {1063-9667},
pages = {406},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812641},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Testing Flash Memories
SN - 1063-9667
SP
EP
A1 - Mohammad Gh. Mohammad,
A1 - Kewal K. Saluja,
A1 - Alex Yap,
PY - 2000
KW - Flash memories
KW - Testing
KW - Disturbances
KW - FG transistor
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Mohammad Gh. Mohammad, University of Wisconsin-Madison
Kewal K. Saluja, University of Wisconsin-Madison
Alex Yap, Motorola
Flash memories can undergo three different types of disturbances, DC-Programming, DC-Erasure, and Drain Disturbance. These faults are specific to flash memories and do not occur in RAMs. In this paper, we discuss these disturbances, their causes, and develop fault models that capture the characteristics of these faults. We present optimal and near optimal algorithms to detect these faults in flash memories.
Index Terms:
Flash memories, Testing, Disturbances, FG transistor
Citation:
Mohammad Gh. Mohammad, Kewal K. Saluja, Alex Yap, "Testing Flash Memories," vlsid, pp.406, 13th International Conference on VLSI Design, 2000
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