With continuous advances in VLSIC technology and customer demands for higher speeds & smaller chips, package parasitic characterization especially capacitive and inductive has become the primary objective in the bench marking and designing stages.The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in high-density IC's by using a test signal (of small known amplitude and frequency) and a D.C. signal along with a Differential circuit.Other measurement techniques such as LCZ and TDR for measuring inductance parameters are faced with limitations of L values greater than 5nH. The Test Signal Injection compliments this method and facilitates measurement of very low L values, especially those encountered in high speed circuits. This technique is applicable in the designing and benchmarking stage and hence is used to model interconnect couplings before packaging and polysilicon layout.An account of interconnect-substrate effects causing displacement currents that result in self-inductive effects is given. Small interconnects have been modeled as lumped elements of a transmission line to form a full system integrity analysis of the Test Signal Injection Method circuitry for circuit simulation using SPICE. A careful simulation procedure was carried out to determine the input parameters of test signal amplitude and frequency to accommodate the parasitics of the interconnect under characterization.