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13th International Conference on VLSI Design
Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
Santanu Dutta, Philips Semiconductors
Deepak Singh, Philips Semiconductors
Essam Abu-Ghoush, Philips Semiconductors
Vijay Mehra, Philips Semiconductors
This paper describes the architecture, functionality, and design of HDVO --- a high definition video co-processor from Philips Semiconductors. The co-processor design is modular and functionally complete, and is intended to be a part of and function as the primary picture/video composition hardware in any media-processor chip targeted at Digital Television (DTV) applications.Essentially a screen-refresh engine, HDVO can mix multiple video and graphics planes and is capable of scaling vertically and horizontally pictures of the highest resolution (1920 x 1080) specified in the DTV standard prescribed by the United States Advanced Television Systems Committee (ATSC). HDVO can efficiently process all (eighteen) ATSC video formats, including video generation for picture-in-picture display, and is currently being used as an on-chip video co-processor in the TM-2700 digital television chip. TM-2700 is the second generation of an architectural family of programmable multimedia processors from Philips Semiconductors and it not only supports all ATSC formats, from standard-definition to wide-angle high-definition video, but has also the power to handle High-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services.
Index Terms:
Digital television, HDTV, video processing, media processor, ATSC standard, picture processing, VLSI design
Citation:
Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra, "Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications," vlsid, pp.350, 13th International Conference on VLSI Design, 2000
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