Automatic Validation Test Generation Using Extracted Control Models

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - Automatic Validation Test Generation Using Extracted Control Models

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Rob Sumners Articles by Jayanta Bhadra Articles by Jacob Abraham

13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Rob Sumners, Jayanta Bhadra, Jacob Abraham, "Automatic Validation Test Generation Using Extracted Control Models," VLSI Design, International Conference on, pp. 312, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812627, author = {Rob Sumners and Jayanta Bhadra and Jacob Abraham}, title = {Automatic Validation Test Generation Using Extracted Control Models}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {312}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812627}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Automatic Validation Test Generation Using Extracted Control Models SN - 1063-9667 SP EP A1 - Rob Sumners, A1 - Jayanta Bhadra, A1 - Jacob Abraham, PY - 2000 KW - validation test KW - automatic test generation KW - abstraction KW - witness generation KW - binary decision diagrams VL - 0 JA - VLSI Design, International Conference on ER -

Rob Sumners, University of Texas at Austin

Jayanta Bhadra, University of Texas at Austin

Jacob Abraham, University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812627

We present a procedure for the automatic generation of tests covering control states of a sequential circuit. The procedure consists of extracting a control model of the circuit under test and then using this model to guide the search for concrete executions or witnesses. We present results of experiments using the procedure on a communication chip from industry as well as an implementation of the ARM 2 processor.

Index Terms:

validation test, automatic test generation, abstraction, witness generation, binary decision diagrams

Citation:

Rob Sumners, Jayanta Bhadra, Jacob Abraham, "Automatic Validation Test Generation Using Extracted Control Models," vlsid, pp.312, 13th International Conference on VLSI Design, 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.