Topological Routing Amidst Polygonal Obstacles

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - Topological Routing Amidst Polygonal Obstacles

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	Similar Articles Articles by Swarup Bhunia Articles by Subhashis Majumder Articles by Ayan Sircar Articles by Susmita Sur-Kolay Articles by Bhargab B. Bhattacharya

13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya, "Topological Routing Amidst Polygonal Obstacles," VLSI Design, International Conference on, pp. 274, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812621, author = {Swarup Bhunia and Subhashis Majumder and Ayan Sircar and Susmita Sur-Kolay and Bhargab B. Bhattacharya}, title = {Topological Routing Amidst Polygonal Obstacles}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {274}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812621}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Topological Routing Amidst Polygonal Obstacles SN - 1063-9667 SP EP A1 - Swarup Bhunia, A1 - Subhashis Majumder, A1 - Ayan Sircar, A1 - Susmita Sur-Kolay, A1 - Bhargab B. Bhattacharya, PY - 2000 VL - 0 JA - VLSI Design, International Conference on ER -

Swarup Bhunia, Delsoft India Pvt. Ltd.

Subhashis Majumder, Delsoft India Pvt. Ltd.

Ayan Sircar, Delsoft India Pvt. Ltd.

Susmita Sur-Kolay, Indian Statistical Institute

Bhargab B. Bhattacharya, Indian Statistical Institute

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812621

This paper presents a fast graph-traversal based greedy approach for solving the problem of topological routing in the presence of polygonal obstacles. The polygonal obstacles represent pre-routed nets or groups of circuit blocks. Routing paths for all the nets are constructed incrementally and concurrently. Design rules for separation are modeled as constraints on edges and vertices. The experimental results obtained are very encouraging.

Citation:

Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya, "Topological Routing Amidst Polygonal Obstacles," vlsid, pp.274, 13th International Conference on VLSI Design, 2000

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