On the Transistor Sizing Problem

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - On the Transistor Sizing Problem

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13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Abhijit Das, "On the Transistor Sizing Problem," VLSI Design, International Conference on, pp. 258, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812618, author = {Abhijit Das}, title = {On the Transistor Sizing Problem}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {258}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812618}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - On the Transistor Sizing Problem SN - 1063-9667 SP EP A1 - Abhijit Das, PY - 2000 KW - Timing Analysis KW - Timing Optimization KW - Transistor Sizing KW - Delay Constraint VL - 0 JA - VLSI Design, International Conference on ER -

Abhijit Das, Motorola India Electronics Limited

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812618

This paper introduces a new transistor sizing technique for timing optimization in a transistor level netlist. Starting from an initial solution, the widths of the transistors in the netlist are tuned iteratively to meet the specified timing constraints. Efficient heuristics to significantly improve the run time performance are outlined. The improvement of timing and area performance are demonstrated with several real circuits.

Index Terms:

Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint

Citation:

Abhijit Das, "On the Transistor Sizing Problem," vlsid, pp.258, 13th International Conference on VLSI Design, 2000

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