This paper proposes a new technique for power optimization during high level synthesis. Specifically, we present a floorplan based Combined Register And Module assignment algorithm, CREAM, for synthesizing low power datapath circuits. The algorithm accepts a scheduled data flow graph and assigns operations to functional units and variables to registers. The operations which have common inputs and are capable of reducing power by mapping to the same functional unit are identified. Further, variables are assigned to registers in such a manner that the unwanted or spurious computations are minimized. During variable assignment, that particular register is selected (based on the floorplan) which has a smaller interconnect length between itself and the functional unit. This optimizes the interconnect power. CREAM has been applied to some high level synthesis benchmarks and the results obtained indicate that power savings up to 43% with an area increase of up to 5.0% is achieved.