Maximizing Wafer Productivity Through Layout Optimization

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	Similar Articles Articles by C. Ouyang Articles by H.T. Heineken Articles by J. Khare Articles by S. Shaikh Articles by M d'Abreu

13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	C. Ouyang, H.T. Heineken, J. Khare, S. Shaikh, M d'Abreu, "Maximizing Wafer Productivity Through Layout Optimization," VLSI Design, International Conference on, pp. 192, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812608, author = {C. Ouyang and H.T. Heineken and J. Khare and S. Shaikh and M d'Abreu}, title = {Maximizing Wafer Productivity Through Layout Optimization}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {192}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812608}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Maximizing Wafer Productivity Through Layout Optimization SN - 1063-9667 SP EP A1 - C. Ouyang, A1 - H.T. Heineken, A1 - J. Khare, A1 - S. Shaikh, A1 - M d'Abreu, PY - 2000 KW - manufacturability KW - design for manufacturability KW - yield KW - wafer productivity KW - die cost KW - interconnect cost VL - 0 JA - VLSI Design, International Conference on ER -

C. Ouyang, Level One Communications, Inc.

H.T. Heineken, Level One Communications, Inc.

J. Khare, Level One Communications, Inc.

S. Shaikh, Level One Communications, Inc.

M d'Abreu, Level One Communications, Inc.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812608

Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4 - 6%. This paper applies DFM to the routing. In particular, this paper analyzes the effects of various routing options on wafer productivity, and shows that if properly applied DFM can lead to a further die cost reduction of 9%.

Index Terms:

manufacturability, design for manufacturability, yield, wafer productivity, die cost, interconnect cost

Citation:

C. Ouyang, H.T. Heineken, J. Khare, S. Shaikh, M d'Abreu, "Maximizing Wafer Productivity Through Layout Optimization," vlsid, pp.192, 13th International Conference on VLSI Design, 2000

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