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13th International Conference on VLSI Design
Manufacturing and Test Considerations in System-On-Chip Designs
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
M. d'Abreu, Level One Communications Inc.
This session describes the impact of cost at four stages in the design cycle - (a) architecture (b) synthesis and (c) layout and (d) test. This will be done using data from example industrial SoC. In addition, methodologies to reduce costs at each of these three stages will be proposed.
Citation:
M. d'Abreu, "Manufacturing and Test Considerations in System-On-Chip Designs," vlsid, pp.176, 13th International Conference on VLSI Design, 2000
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