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13th International Conference on VLSI Design
Status Condition Analysis during Data Path Verification of Sequential Circuits
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
ASCII Text
x 
 
D Sarkar, "Status Condition Analysis during Data Path Verification of Sequential Circuits," VLSI Design, International Conference on, pp. 70, 13th International Conference on VLSI Design, 2000.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.2000.812587,
author = {D Sarkar},
title = {Status Condition Analysis during Data Path Verification of Sequential Circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2000},
issn = {1063-9667},
pages = {70},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812587},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Status Condition Analysis during Data Path Verification of Sequential Circuits
SN - 1063-9667
SP
EP
A1 - D Sarkar,
PY - 2000
VL - 0
JA - VLSI Design, International Conference on
ER -
 
D Sarkar, Indian Institute of Technology
A control path data path partition based sequential circuit verification scheme can avoid the state explosion problem. Of the two broad tasks involved in data path verification namely, register transfer operation analysis and status condition analysis, the second one is described. The issues addressed are (i) time expended in status detection and (ii) completeness of the analysis function. A status analyzer, based on a simplifying assumption, has been presented.
Citation:
D Sarkar, "Status Condition Analysis during Data Path Verification of Sequential Circuits," vlsid, pp.70, 13th International Conference on VLSI Design, 2000
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