A Semi-Digital Delay Locked Loop for Clock Skew Minimization

V
VLSID
1999
12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Abstract - A Semi-Digital Delay Locked Loop for Clock Skew Minimization

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Joonbae Park Articles by Yido Koo Articles by Wonchan Kim

12th International Conference on VLSI Design - 'VLSI for the Information Appliance'

Goa, India

January 10-January 13

ISBN: 0-7695-0013-7

	ASCII Text	x
	Joonbae Park, Yido Koo, Wonchan Kim, "A Semi-Digital Delay Locked Loop for Clock Skew Minimization," VLSI Design, International Conference on, pp. 584, 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', 1999.

	BibTex	x
	@article{ 10.1109/ICVD.1999.745218, author = {Joonbae Park and Yido Koo and Wonchan Kim}, title = {A Semi-Digital Delay Locked Loop for Clock Skew Minimization}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-9667}, pages = {584}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745218}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Semi-Digital Delay Locked Loop for Clock Skew Minimization SN - 1063-9667 SP EP A1 - Joonbae Park, A1 - Yido Koo, A1 - Wonchan Kim, PY - 1999 VL - 0 JA - VLSI Design, International Conference on ER -

Joonbae Park, Seoul National University

Yido Koo, Seoul National University

Wonchan Kim, Seoul National University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745218

A two step approach for fast locking of a DLL(Delay-Locked-Loop) circuit will be discussed. The locking process consists of two steps; the coarse tuning in digital domain by tapping a delay position for fast coarse locking, and the accurate phase synchronization between the external clock and the interrnal clock in analog operation mode. With this two step approach, fast locking and low phase error can be simultaneously achieved.

Citation:

Joonbae Park, Yido Koo, Wonchan Kim, "A Semi-Digital Delay Locked Loop for Clock Skew Minimization," vlsid, pp.584, 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.