A complete one-to-one characterization of path delay fault testability for a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent unfolded circuit. The unfolded circuit is obtained simply by replicating the cone feeding each internal fanout stem line, thereby making it internally fanout free. Unfolding preserves both functional, and structural characteristics of the original circuit. Earlier results describing correlation of path delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. We show that a path delay fault (rising or falling) is testable iff certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path delay faults related to testability under various classification schemes are interpreted using the stuck-at fault model alone in the unfolded circuit. The results unify most of the existing concepts, provide a better understanding of path delay faults in logic circuits, and have potential applications in identification of false paths.