Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs

V
VLSID
1999
12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Abstract - Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs

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	Similar Articles Articles by D.V.R. Murthy Articles by S. Ramachandran Articles by S. Srinivasan

12th International Conference on VLSI Design - 'VLSI for the Information Appliance'

Goa, India

January 10-January 13

ISBN: 0-7695-0013-7

	ASCII Text	x
	D.V.R. Murthy, S. Ramachandran, S. Srinivasan, "Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs," VLSI Design, International Conference on, pp. 336, 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', 1999.

	BibTex	x
	@article{ 10.1109/ICVD.1999.745178, author = {D.V.R. Murthy and S. Ramachandran and S. Srinivasan}, title = {Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-9667}, pages = {336}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745178}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs SN - 1063-9667 SP EP A1 - D.V.R. Murthy, A1 - S. Ramachandran, A1 - S. Srinivasan, PY - 1999 VL - 0 JA - VLSI Design, International Conference on ER -

D.V.R. Murthy, Indian Institute of Technology

S. Ramachandran, Indian Institute of Technology

S. Srinivasan, Indian Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745178

A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it's architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size 512 X 512 pixels at rates of 25 frames per second. The chip set offers device independent design and can be used in conjunction with other processors. The algorithm implemented can be easily modified and remapped as per needs with a minimum of effort since the architecture is realized using modular Hardware Description Language (HDL). The hardware complexity and accuracy of the proposed DCT processor compare favourably with those of other known implementation techniques.

Citation:

D.V.R. Murthy, S. Ramachandran, S. Srinivasan, "Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs," vlsid, pp.336, 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', 1999

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