Eleventh International Conference on VLSI Design: VLSI for Signal Processing
A Fast Two-level Logic Minimizer
India
January 04-January 07
ISBN: 0-8186-8224-8
We present NEWMIN, an efficient cube-based algorithm for minimization of single Boolean functions. The salient features of the algorithm are that it does not generate all the prime cubes, and highly efficient heuristics are used to obtain a minimal SPC cover. This leads to savings in computation time and as well as reduces the cost of the solution for some classes of functions. The performance of a prototype implementation of NEWMIN is compared to that of ESPRESSO, the best known logic minimizer currently available. Our algorithm efficiently handles Achilles' heel functions which ESPRESSO finds difficult. Further, as is evident from the results, NEWMIN exhibits better performance on several classes of functions such as parity functions, cyclic functions and most randomly generated functions.
Index Terms:
logic minimization algorithms, logic synthesis
Citation:
P. Srinivasa Rao, James Jacob, "A Fast Two-level Logic Minimizer," vlsid, pp.528, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998