Wave pipelining is a digital design technique that can be applied to combinational logic circuits to increase the throughput of the system without increasing the demand for additional storage space and power. The internal capacitances of the gates are used for storage. Gate library for wave pipelining should have input inde pendent, functionality independent and load capacitance indepen dent delays. Conventional static CMOS has input dependent delay and is not suitable for wave pipelining forcing the designers to look for alternative solutions. The wave pipelining design technique requires path delay equalization along all paths from the input to output. Delay balancing is achieved in a design by means of a pro cess called "tuning". Rough tuning is performed to balance all the paths with the same number of gates and fine tuning is done to adjust the sizes of transistors in the driver gate for different loads. The design styles that have been proposed for wave pipelining have unbalanced input loading and this results in complex fine tuning process. In this paper, double pass transistor logic style(DPL) gates are modified to form a library of basic gates having perfect input symmetry. The balanced input capacitance of the DPL gates makes the fine tuning process less computation intensive. Performance of the basic gates of all wave pipeline logic styles are presented and compared. A fine tuning method is presented in this paper for wave pipeline designs with DPL logic. An 8 bit adder was designed and the results are presented to show the performance efficiency of dou ble pass transistor logic for wave pipelining.