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Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Path Delay Testing: Variable-Clock Versus Rated-Clock
India
January 04-January 07
ISBN: 0-8186-8224-8
Subhashis Majumder, Rutgers University
Michael L. Bushnell, Rutgers University
There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply- testable paths, and hence corresponds to non-robust detection.
Index Terms:
Delay testing, path delay faults, rated-clock testing, sequential circuit test, slow-clock testing.
Citation:
Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal, "Path Delay Testing: Variable-Clock Versus Rated-Clock," vlsid, pp.470, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998
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