Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis

V
VLSID
1998
Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Abstract - Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis

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Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Pradeep Prabhakaran, Prithviraj Banerjee, "Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis," VLSI Design, International Conference on, pp. 428, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646645, author = {Pradeep Prabhakaran and Prithviraj Banerjee}, title = {Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {428}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646645}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis SN - 1063-9667 SP EP A1 - Pradeep Prabhakaran, A1 - Prithviraj Banerjee, PY - 1998 KW - High-level synthesis KW - timing driven synthesis KW - floorplanning. VL - 0 JA - VLSI Design, International Conference on ER -

Pradeep Prabhakaran, University of Illinois, Urbana

Prithviraj Banerjee, Northwestern University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646645

With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexor and register areas and delays.

Index Terms:

High-level synthesis, timing driven synthesis, floorplanning.

Citation:

Pradeep Prabhakaran, Prithviraj Banerjee, "Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis," vlsid, pp.428, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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