Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Amey Karkare Articles by Manoj Singla Articles by Ajai Jain

Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Amey Karkare, Manoj Singla, Ajai Jain, "Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit," VLSI Design, International Conference on, pp. 370, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646635, author = {Amey Karkare and Manoj Singla and Ajai Jain}, title = {Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {370}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646635}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit SN - 1063-9667 SP EP A1 - Amey Karkare, A1 - Manoj Singla, A1 - Ajai Jain, PY - 1998 KW - Testability KW - DFT KW - Delay Faults KW - Testability Preserving Transformations KW - Testability Enhancing Transformations VL - 0 JA - VLSI Design, International Conference on ER -

Amey Karkare, Indian Institute of Technology Kanpur

Manoj Singla, Indian Institute of Technology Kanpur

Ajai Jain, Indian Institute of Technology Kanpur

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646635

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).

Index Terms:

Testability, DFT, Delay Faults, Testability Preserving Transformations, Testability Enhancing Transformations

Citation:

Amey Karkare, Manoj Singla, Ajai Jain, "Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit," vlsid, pp.370, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.