VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay

V
VLSID
1998
Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Abstract - VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay

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	Similar Articles Articles by S.K. Misra Articles by R.K. Kolagotla Articles by H.R. Srinivas Articles by J.C. Mo Articles by M.S. Diamondstein

Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	S.K. Misra, R.K. Kolagotla, H.R. Srinivas, J.C. Mo, M.S. Diamondstein, "VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay," VLSI Design, International Conference on, pp. 326, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646627, author = {S.K. Misra and R.K. Kolagotla and H.R. Srinivas and J.C. Mo and M.S. Diamondstein}, title = {VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {326}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646627}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay SN - 1063-9667 SP EP A1 - S.K. Misra, A1 - R.K. Kolagotla, A1 - H.R. Srinivas, A1 - J.C. Mo, A1 - M.S. Diamondstein, PY - 1998 KW - Fast counter KW - VLSI KW - Testability VL - 0 JA - VLSI Design, International Conference on ER -

S.K. Misra, Bell-Labs, Lucent Technologies

R.K. Kolagotla, Bell-Labs, Lucent Technologies

H.R. Srinivas, Bell-Labs, Lucent Technologies

J.C. Mo, Bell-Labs, Lucent Technologies

M.S. Diamondstein, Bell-Labs, Lucent Technologies

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646627

We describe the VLSI implementation of a fully testable high-speed binary synchronous counter that is pre-loadable and auto-reloadable. High-speed operation is achieved by precomputing the carry independent terms and by using the carry signal as a selector in the last gate before the storage latch. An efficient test logic is used that has minimal impact on the counter speed during normal operation, and significantly reduces the test time and test cost.

Index Terms:

Fast counter, VLSI, Testability

Citation:

S.K. Misra, R.K. Kolagotla, H.R. Srinivas, J.C. Mo, M.S. Diamondstein, "VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay," vlsid, pp.326, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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