Timing Driven Multi-FPGA Board Partitioning

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	Similar Articles Articles by Raghu Burra Articles by Dinesh Bhatia

Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Raghu Burra, Dinesh Bhatia, "Timing Driven Multi-FPGA Board Partitioning," VLSI Design, International Conference on, pp. 234, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646609, author = {Raghu Burra and Dinesh Bhatia}, title = {Timing Driven Multi-FPGA Board Partitioning}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {234}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646609}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Timing Driven Multi-FPGA Board Partitioning SN - 1063-9667 SP EP A1 - Raghu Burra, A1 - Dinesh Bhatia, PY - 1998 VL - 0 JA - VLSI Design, International Conference on ER -

Raghu Burra, University of Cincinnati

Dinesh Bhatia, University of Cincinnati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646609

System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by \cite{alpert} and retiming \cite{saxe}. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.

Citation:

Raghu Burra, Dinesh Bhatia, "Timing Driven Multi-FPGA Board Partitioning," vlsid, pp.234, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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