Optimizing Logic Design Using Boolean Transforms

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Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Pramit Chavda, James Jacob, Vishwani D. Agrawal, "Optimizing Logic Design Using Boolean Transforms," VLSI Design, International Conference on, pp. 218, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646605, author = {Pramit Chavda and James Jacob and Vishwani D. Agrawal}, title = {Optimizing Logic Design Using Boolean Transforms}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {218}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646605}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Optimizing Logic Design Using Boolean Transforms SN - 1063-9667 SP EP A1 - Pramit Chavda, A1 - James Jacob, A1 - Vishwani D. Agrawal, PY - 1998 KW - Boolean functions KW - logic design KW - logic synthesis KW - multi-level synthesis. VL - 0 JA - VLSI Design, International Conference on ER -

Pramit Chavda, Tata-IBM

James Jacob, Nortel

Vishwani D. Agrawal, Bell Labs

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646605

When a Boolean function is transformed by exclusive-OR with a suitably selected transform function, the new function is often synthesized with significantly reduced hardware. The transform function is separately synthesized and the original function is recovered as an exclusive-OR of the two functions. We select the transform to reduce the number of cubes in the function to be synthesized. The function is represented as a Shannon expansion about selected variables. A transform function is constructed such that a selected set of cofactors is complemented to minimize the overall number of cubes. Examples of single-output functions show an average area reduction of 19%. For a multiple-output function, transformations can be customized for each output.

Index Terms:

Boolean functions, logic design, logic synthesis, multi-level synthesis.

Citation:

Pramit Chavda, James Jacob, Vishwani D. Agrawal, "Optimizing Logic Design Using Boolean Transforms," vlsid, pp.218, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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