Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults

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Eleventh International Conference on VLSI Design: VLSI for Signal Processing

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya, "Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults," VLSI Design, International Conference on, pp. 205, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646603, author = {Debesh K. Das and Indrajit Chaudhuri and Bhargab B. Bhattacharya}, title = {Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {205}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646603}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults SN - 1063-9667 SP EP A1 - Debesh K. Das, A1 - Indrajit Chaudhuri, A1 - Bhargab B. Bhattacharya, PY - 1998 KW - Built-in self-test KW - delay faults KW - robust testing KW - TPG KW - two-pattern tests. VL - 0 JA - VLSI Design, International Conference on ER -

Debesh K. Das, Jadavpur University

Indrajit Chaudhuri, Mentor Graphics Corporation

Bhargab B. Bhattacharya, Indian Statistical Institute

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646603

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2n +1), that includes all n.2n single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2n +1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.

Index Terms:

Built-in self-test, delay faults, robust testing, TPG, two-pattern tests.

Citation:

Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya, "Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults," vlsid, pp.205, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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