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Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters
India
January 04-January 07
ISBN: 0-8186-8224-8
Mahesh Mehendale, Texas Instruments Ltd.
Somdipta Basu Roy, Texas Instruments Ltd.
S.D. Sherlekar, Indian Institute of Technology
G. Venkatesh, Indian Institute of Technology
Techniques based on common sub-computation extraction can be used to minimize number of additions in the multiplier-less implementations of Finite Impulse Response (FIR) filters. We present two types of coefficient transforms which used in conjunction with these techniques enable area-efficient realization of multiplier-less FIR filters.Number theoretic transforms that use redundant binary representations such as Canonical Sign Digit (CSD). Signal Flow Graph transformations that modify the coefficient values while retaining the output functionality. We demonstrate this with results of 6 different coefficient transforms for 14 low pass FIR filters with number of taps ranging from 16 to 128.
Index Terms:
FIR Filters, High Level Synthesis-Transformations
Citation:
Mahesh Mehendale, Somdipta Basu Roy, S.D. Sherlekar, G. Venkatesh, "Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters," vlsid, pp.110, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998
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