BIST (Built-In-Self-Test) has received significant attention in, both academic and industrial circles, as id offers solutions to several major testing problems at both chip level as well as system level. However most of the commercial RTL synthesis tools to date, used by designers offer full scan and/or partial scan solutions for testing the synthesized netlists thus making the effectiveness of the testing scheme totally governed by the effectiveness of ATPGs in generating the necessary test patterns to ensure high testability. Designing a sequential ATPG to ensure high testability of FSMs in all types of RTL designs is a complex task. In this work, we have proposed a Cellular Automata (CA) based BIST scheme for testing FSMs in the netlists generated after synthesizing a VERILOG/VHDL description. The scheme makes the FSMs fully testable for a single stuck-at fault model. We have integrated this scheme for testing control part into SYNERGY which is the Cadence RTL synthesis tool. The generated netlists have been simulated using VERILOG simulator of Cadence for verifying the functional correctness. The experimental results on a typical target library have shown a BIST area overhead of around 10% in most of the designs and 13% and 17% in two designs.