Impact of Partial Reset on Fault Independent Testing and BIST

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Impact of Partial Reset on Fault Independent Testing and BIST

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	H. Nguyen, A. Chatterjee, R. Roy, "Impact of Partial Reset on Fault Independent Testing and BIST," VLSI Design, International Conference on, pp. 537, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568202, author = {H. Nguyen and A. Chatterjee and R. Roy}, title = {Impact of Partial Reset on Fault Independent Testing and BIST}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {537}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568202}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Impact of Partial Reset on Fault Independent Testing and BIST SN - 1063-9667 SP EP A1 - H. Nguyen, A1 - A. Chatterjee, A1 - R. Roy, PY - 1997 KW - fault diagnosis KW - partial reset KW - fault independent testing KW - BIST KW - deterministic test generation KW - sequential circuits KW - fault propagation analysis KW - circuit flip-flops KW - test input vectors KW - random pattern testing VL - 0 JA - VLSI Design, International Conference on ER -

H. Nguyen, Georgia Inst. of Technol., Atlanta, GA, USA

A. Chatterjee, Georgia Inst. of Technol., Atlanta, GA, USA

R. Roy, Georgia Inst. of Technol., Atlanta, GA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568202

Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/reset) is performed periodically while the test input vectors to the sequential circuit are applied. An average improvement of 15% in fault-coverage has been obtained for circuits resistant to random pattern testing.

Index Terms:

fault diagnosis, partial reset, fault independent testing, BIST, deterministic test generation, sequential circuits, fault propagation analysis, circuit flip-flops, test input vectors, random pattern testing

Citation:

H. Nguyen, A. Chatterjee, R. Roy, "Impact of Partial Reset on Fault Independent Testing and BIST," vlsid, pp.537, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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