Parallel Decoder for Cellular Automata Based Byte Error Correcting Code

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Parallel Decoder for Cellular Automata Based Byte Error Correcting Code

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	Similar Articles Articles by S. Chattopadhyay Articles by P. Pal Chaudhuri

Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Parallel Decoder for Cellular Automata Based Byte Error Correcting Code (PDF)

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	S. Chattopadhyay, P. Pal Chaudhuri, "Parallel Decoder for Cellular Automata Based Byte Error Correcting Code," VLSI Design, International Conference on, pp. 527, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568197, author = {S. Chattopadhyay and P. Pal Chaudhuri}, title = {Parallel Decoder for Cellular Automata Based Byte Error Correcting Code}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {527}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568197}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Parallel Decoder for Cellular Automata Based Byte Error Correcting Code SN - 1063-9667 SP EP A1 - S. Chattopadhyay, A1 - P. Pal Chaudhuri, PY - 1997 KW - cellular automata KW - parallel decoder KW - cellular automata KW - byte error correcting code KW - design KW - SbEC/DbED code KW - DbEC/DbED code KW - Reed-Solomon code VL - 0 JA - VLSI Design, International Conference on ER -

S. Chattopadhyay, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India

P. Pal Chaudhuri, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568197

In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional Reed-Solomon code.

Index Terms:

cellular automata, parallel decoder, cellular automata, byte error correcting code, design, SbEC/DbED code, DbEC/DbED code, Reed-Solomon code

Citation:

S. Chattopadhyay, P. Pal Chaudhuri, "Parallel Decoder for Cellular Automata Based Byte Error Correcting Code," vlsid, pp.527, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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