In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional Reed-Solomon code.
Index Terms:
cellular automata, parallel decoder, cellular automata, byte error correcting code, design, SbEC/DbED code, DbEC/DbED code, Reed-Solomon code
Citation:
S. Chattopadhyay, P. Pal Chaudhuri, "Parallel Decoder for Cellular Automata Based Byte Error Correcting Code," vlsid, pp.527, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997