A 2.5 V 10 bit SAR ADC

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

A 2.5 V 10 bit SAR ADC (PDF)

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	S. Mukherjee, C. Srinivasan, V. Pawar, S. Mathur, K. Godbole, E. Soenen, "A 2.5 V 10 bit SAR ADC," VLSI Design, International Conference on, pp. 525, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568196, author = {S. Mukherjee and C. Srinivasan and V. Pawar and S. Mathur and K. Godbole and E. Soenen}, title = {A 2.5 V 10 bit SAR ADC}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {525}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568196}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A 2.5 V 10 bit SAR ADC SN - 1063-9667 SP EP A1 - S. Mukherjee, A1 - C. Srinivasan, A1 - V. Pawar, A1 - S. Mathur, A1 - K. Godbole, A1 - E. Soenen, PY - 1997 KW - sample and hold circuits KW - SAR ADC KW - CMOS process KW - metal-poly capacitor KW - low voltage sampling circuit KW - high speed comparator design KW - successive approximation KW - 10 bit KW - 2.5 to 5.5 V VL - 0 JA - VLSI Design, International Conference on ER -

S. Mukherjee, Texas Instrum. India Ltd., Bangalore, India

C. Srinivasan, Texas Instrum. India Ltd., Bangalore, India

V. Pawar, Texas Instrum. India Ltd., Bangalore, India

S. Mathur, Texas Instrum. India Ltd., Bangalore, India

K. Godbole, Texas Instrum. India Ltd., Bangalore, India

E. Soenen, Texas Instrum. India Ltd., Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568196

Presented here is a 10 bit SAR ADC working over a wide supply range of 5.5 V to 2.5 V. The circuit is built in a CMOS process with Metal-Poly capacitors. Issues related to low voltage sampling circuitry design and low voltage high speed comparator design are discussed. Silicon evaluation results are presented.

Index Terms:

sample and hold circuits, SAR ADC, CMOS process, metal-poly capacitor, low voltage sampling circuit, high speed comparator design, successive approximation, 10 bit, 2.5 to 5.5 V

Citation:

S. Mukherjee, C. Srinivasan, V. Pawar, S. Mathur, K. Godbole, E. Soenen, "A 2.5 V 10 bit SAR ADC," vlsid, pp.525, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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