FPGA Implementation of Median Filter

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

FPGA Implementation of Median Filter (PDF)

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	R. Maheshwari, S.S.S.P. Rao, E.G. Poonach, "FPGA Implementation of Median Filter," VLSI Design, International Conference on, pp. 523, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568194, author = {R. Maheshwari and S.S.S.P. Rao and E.G. Poonach}, title = {FPGA Implementation of Median Filter}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {523}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568194}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - FPGA Implementation of Median Filter SN - 1063-9667 SP EP A1 - R. Maheshwari, A1 - S.S.S.P. Rao, A1 - E.G. Poonach, PY - 1997 KW - field programmable gate arrays KW - algorithm KW - real time median filter KW - design KW - Xilinx XC4010 FPGA chip KW - sliding window VL - 0 JA - VLSI Design, International Conference on ER -

R. Maheshwari, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India

S.S.S.P. Rao, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India

E.G. Poonach, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568194

This paper gives the algorithm and implementation details of a sliding real time 3/spl times/3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques.

Index Terms:

field programmable gate arrays, algorithm, real time median filter, design, Xilinx XC4010 FPGA chip, sliding window

Citation:

R. Maheshwari, S.S.S.P. Rao, E.G. Poonach, "FPGA Implementation of Median Filter," vlsid, pp.523, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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