Faster Fault Simulation Through Distributed Computing

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Faster Fault Simulation Through Distributed Computing

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	Similar Articles Articles by C.P. Ravikumar Articles by V. Jain Articles by A. Dod

Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	C.P. Ravikumar, V. Jain, A. Dod, "Faster Fault Simulation Through Distributed Computing," VLSI Design, International Conference on, pp. 482, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568181, author = {C.P. Ravikumar and V. Jain and A. Dod}, title = {Faster Fault Simulation Through Distributed Computing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {482}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568181}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Faster Fault Simulation Through Distributed Computing SN - 1063-9667 SP EP A1 - C.P. Ravikumar, A1 - V. Jain, A1 - A. Dod, PY - 1997 KW - combinational circuits KW - combinational fault simulation KW - distributed algorithms KW - distributed computing KW - classical stuck-at fault model KW - Sun workstation network KW - parallel virtual machine environment KW - test set partition KW - fault set partition KW - sequential algorithm KW - path compression technique KW - ISCAS '85 benchmark circuits VL - 0 JA - VLSI Design, International Conference on ER -

C.P. Ravikumar, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

V. Jain, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

A. Dod, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568181

In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS '85 benchmark circuits.

Index Terms:

combinational circuits, combinational fault simulation, distributed algorithms, distributed computing, classical stuck-at fault model, Sun workstation network, parallel virtual machine environment, test set partition, fault set partition, sequential algorithm, path compression technique, ISCAS '85 benchmark circuits

Citation:

C.P. Ravikumar, V. Jain, A. Dod, "Faster Fault Simulation Through Distributed Computing," vlsid, pp.482, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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