Micropipeline Architecture for Multiplier-less FIR Filters

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Micropipeline Architecture for Multiplier-less FIR Filters

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	Similar Articles Articles by S. Nooshabadi Articles by J. A. Montiel-Nelson Articles by G. S. Visweswaran Articles by D. Nagchoudhurhi

Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	S. Nooshabadi, J. A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhurhi, "Micropipeline Architecture for Multiplier-less FIR Filters," VLSI Design, International Conference on, pp. 451, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568175, author = {S. Nooshabadi and J. A. Montiel-Nelson and G. S. Visweswaran and D. Nagchoudhurhi}, title = {Micropipeline Architecture for Multiplier-less FIR Filters}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {451}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568175}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Micropipeline Architecture for Multiplier-less FIR Filters SN - 1063-9667 SP EP A1 - S. Nooshabadi, A1 - J. A. Montiel-Nelson, A1 - G. S. Visweswaran, A1 - D. Nagchoudhurhi, PY - 1997 VL - 0 JA - VLSI Design, International Conference on ER -

S. Nooshabadi, Northern Territory University

J. A. Montiel-Nelson, Universidad de Las Palmas de Gran Canaria

G. S. Visweswaran, Indian Institute of Technology, Delhi

D. Nagchoudhurhi, Indian Institute of Technology, Delhi

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568175

In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropiplined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.

Citation:

S. Nooshabadi, J. A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhurhi, "Micropipeline Architecture for Multiplier-less FIR Filters," vlsid, pp.451, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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