loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Novel Reconfigurable Co-Processor Architecture
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
ASCII Text
x 
 
Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar, "A Novel Reconfigurable Co-Processor Architecture," VLSI Design, International Conference on, pp. 370, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1997.568155,
author = {Gaurav Aggarwal and Nitin Thaper and Kamal Aggarwal and M. Balakrishnan and Shashi Kumar},
title = {A Novel Reconfigurable Co-Processor Architecture},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1997},
issn = {1063-9667},
pages = {370},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568155},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Novel Reconfigurable Co-Processor Architecture
SN - 1063-9667
SP
EP
A1 - Gaurav Aggarwal,
A1 - Nitin Thaper,
A1 - Kamal Aggarwal,
A1 - M. Balakrishnan,
A1 - Shashi Kumar,
PY - 1997
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Gaurav Aggarwal, Indian Institute of Technology
Nitin Thaper, Indian Institute of Technology
Kamal Aggarwal, Indian Institute of Technology
M. Balakrishnan, Indian Institute of Technology
Shashi Kumar, Indian Institute of Technology
Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, "hardwired" and cannot be used for a new function. In this paper, we discuss the design considerations and parameters of a general purpose reconfigurable co-processor. We also propose architecture of such a co-processor and discuss its implementation issues. The concept of a reconfigurable co-processor has become feasible because of the availability of static RAM based FPGAs. The key architectural features of our system are: scalable topology, shared memory space between the main processor and co-processor and efficient reconfigurability. A small prototype of the system has been implemented. We have demonstrated a two orders of speedup using our system over pure software solutions for a set of compute intensive applications.
Citation:
Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar, "A Novel Reconfigurable Co-Processor Architecture," vlsid, pp.370, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
Usage of this product signifies your acceptance of the Terms of Use.