Asynchronous Implementation of Synchronous Esterel Specifications

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	Similar Articles Articles by Raj S Mitra Articles by Bishnupriya Bhattacharya Articles by Luciano Lavagno

Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	Raj S Mitra, Bishnupriya Bhattacharya, Luciano Lavagno, "Asynchronous Implementation of Synchronous Esterel Specifications," VLSI Design, International Conference on, pp. 348, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568106, author = {Raj S Mitra and Bishnupriya Bhattacharya and Luciano Lavagno}, title = {Asynchronous Implementation of Synchronous Esterel Specifications}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {348}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568106}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Asynchronous Implementation of Synchronous Esterel Specifications SN - 1063-9667 SP EP A1 - Raj S Mitra, A1 - Bishnupriya Bhattacharya, A1 - Luciano Lavagno, PY - 1997 KW - Embedded Systems KW - Executable Specifications KW - Hardware Software Codesign VL - 0 JA - VLSI Design, International Conference on ER -

Raj S Mitra, Cadence Design Systems Pvt Ltd

Bishnupriya Bhattacharya, Cadence Design Systems Pvt Ltd

Luciano Lavagno, Cadence Berkeley Labs

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568106

The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However, for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm, so that the user is aware of the executable semantics that he should expect.

Index Terms:

Embedded Systems, Executable Specifications, Hardware Software Codesign

Citation:

Raj S Mitra, Bishnupriya Bhattacharya, Luciano Lavagno, "Asynchronous Implementation of Synchronous Esterel Specifications," vlsid, pp.348, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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