Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection latency since it is not until the signatures are scanned out and compared off-chip that a fault become apparent. Aliasing, which is a fallout of long detection latency, is a serious problem. In [1], we proposed an improved BIST architecture which supports on-chip comparison of multiple signatures to minimize the probability of aliasing and total test time. In [2], we quantified the aliasing probability of the "Multiple On-chip Signature Comparison scheme" (MOSC) scheme proposed in [1]. In this paper, we describe an efficient implementation of the MOSC test architecture and report results on several benchmark circuits. We describe different optimization methods to reduce the overall test control area.