Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	D. Bhattacharya, S. Freeman, W. Lin, "Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit," VLSI Design, International Conference on, pp. 289, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568092, author = {D. Bhattacharya and S. Freeman and W. Lin}, title = {Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {289}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568092}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit SN - 1063-9667 SP EP A1 - D. Bhattacharya, A1 - S. Freeman, A1 - W. Lin, PY - 1997 KW - design for testability KW - test hardware optimisation KW - at-speed testing KW - datapaths KW - integrated circuit KW - representation method KW - test template representation KW - analysis technique KW - test logic overhead minimisation VL - 0 JA - VLSI Design, International Conference on ER -

D. Bhattacharya, Texas Instruments, USA

S. Freeman, Sarnoff Research Center, USA

W. Lin, Sarnoff Research Center, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568092

In this paper, we introduce a new representation method for datapath tests-called test template representation-and also introduce a new analysis technique to minimize the test logic overhead, through careful processing of the test templates. The resultant test structures represent the next systematic step beyond the multiplexer bypass method commonly found in commercial test tools.

Index Terms:

design for testability, test hardware optimisation, at-speed testing, datapaths, integrated circuit, representation method, test template representation, analysis technique, test logic overhead minimisation

Citation:

D. Bhattacharya, S. Freeman, W. Lin, "Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit," vlsid, pp.289, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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