Tenth International Conference on VLSI Design: VLSI in Multimedia Applications Sequential Circuit Testing: From DFT to SFT Hyderabad, India January 04-January 07 ISBN: 0-8186-7755-4
Sequential circuit testing is an active research area due to its applicability, its practicality, and its complexity. This paper gives an overview of the sequential automatic test pattern generation approaches and the classical and more recent design-for-testability methods. However, recent trend is to move towards synthesis-for-testability (SFT) approach. In this paper, we describe some of the work done by others as well as our current research using SFT techniques. In particular, the ability to perform SFT on large sequential circuits is discussed.
Index Terms:
logic testing, sequential circuit testing, DFT techniques, automatic test pattern generation, design-for-testability methods, synthesis-for-testability, SFT techniques, large sequential circuits, ATPG
Citation:
R.M. Chou, K.K. Saluja, "Sequential Circuit Testing: From DFT to SFT," vlsid, pp.274, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb