Design of a VLSI Hardware PET Decoder

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	G. Ascia, V. Catania, G. Ficili, "Design of a VLSI Hardware PET Decoder," VLSI Design, International Conference on, pp. 253, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568085, author = {G. Ascia and V. Catania and G. Ficili}, title = {Design of a VLSI Hardware PET Decoder}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {253}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568085}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of a VLSI Hardware PET Decoder SN - 1063-9667 SP EP A1 - G. Ascia, A1 - V. Catania, A1 - G. Ficili, PY - 1997 VL - 0 JA - VLSI Design, International Conference on ER -

G. Ascia, Universita' di Catania

V. Catania, Universita' di Catania

G. Ficili, Universita' di Catania

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568085

In this paper we present the design of a hardware architecture for real-time PET (Priority Encoding Transmission) decoding of MPEG-1 messages. The main features of the decoder are: pipeline architecture and parallelism in the execution of some critical phases in the decoding process. The estimated clock frequency is 50 MHz with a required silicon area of about 35 mm2. The total latency introduced to decode an MPEG-1 GOP made up of 30 frames, each of 320X240 pixels, is about 40 ms.

Citation:

G. Ascia, V. Catania, G. Ficili, "Design of a VLSI Hardware PET Decoder," vlsid, pp.253, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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