Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	S. Harikumer, S. Kumar, "Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation," VLSI Design, International Conference on, pp. 239, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568082, author = {S. Harikumer and S. Kumar}, title = {Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {239}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568082}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation SN - 1063-9667 SP EP A1 - S. Harikumer, A1 - S. Kumar, PY - 1997 KW - logic CAD KW - multiobjective search based algorithms KW - circuit partitioning problem KW - logic simulation acceleration KW - FPGA KW - hardware emulation KW - reconfigurable systems KW - resource constraints KW - approximate algorithms KW - optimal algorithms VL - 0 JA - VLSI Design, International Conference on ER -

S. Harikumer, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India

S. Kumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568082

Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems (RS) built using FPGA's offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose.

Index Terms:

logic CAD, multiobjective search based algorithms, circuit partitioning problem, logic simulation acceleration, FPGA, hardware emulation, reconfigurable systems, resource constraints, approximate algorithms, optimal algorithms

Citation:

S. Harikumer, S. Kumar, "Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation," vlsid, pp.239, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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