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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
S. Ramanathan, Indian Institute of Science
V. Visvanathan, Indian Institute of Science
In this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is then extended to derive a configurable processor array (CPA), which is configurable for filter order, sample period and power reduction factor. The hardware overhead incurred for configurability is minimal.
Citation:
S. Ramanathan, V. Visvanathan, "Low-Power Configurable Processor Array for DLMS Adaptive Filtering," vlsid, pp.198, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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