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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Dynamic Power Management for Microprocessors: A Case Study
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
Vivek Tiwari, Intel Corp., Santa Clara, CA, USA
Ryan Donnelly, Intel Corp., Santa Clara, CA, USA
Sharad Malik, Intel Corp., Santa Clara, CA, USA
Ricardo Gonzalez, Intel Corp., Santa Clara, CA, USA
Dynamic power management is one of the most popular and successful low power design techniques in commercial integrated circuits, especially microprocessors. However, despite its significance, relatively little has been published about it. The purpose of this paper is to provide an open discussion of the application of dynamic power management for a real microprocessor. TORCH, a statically scheduled superscalar microprocessor, is chosen for this purpose. We describe several techniques that we classify as dynamic power management-techniques aimed at reducing the power wasted in unnecessary circuit activity in the design. Some of the techniques have been used before for low power designs. Some others are new and it is demonstrated that significant power savings are achieved with these as well. We provide design details to illustrate the application of instances of all dynamic power management techniques for TORCH. Using a combination of techniques, the power consumption is reduced by about 23%. We hope that this study would lead to a wider recognition of dynamic power management as a very effective and practical power reduction technique.
Index Terms:
microprocessor chips, dynamic power management, microprocessor design, low power design technique, integrated circuits, TORCH architecture, statically scheduled superscalar microprocessor, power reduction technique, VERILOG simulation
Citation:
Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez, "Dynamic Power Management for Microprocessors: A Case Study," vlsid, pp.185, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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