Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by M. Vootukuru Articles by R. Vemuri Articles by N. Kumar

Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	M. Vootukuru, R. Vemuri, N. Kumar, "Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs," VLSI Design, International Conference on, pp. 140, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568066, author = {M. Vootukuru and R. Vemuri and N. Kumar}, title = {Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {140}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568066}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs SN - 1063-9667 SP EP A1 - M. Vootukuru, A1 - R. Vemuri, A1 - N. Kumar, PY - 1997 KW - logic partitioning KW - resource constrained RTL partitioning KW - multi-FPGA designs KW - register level designs KW - multiple FPGA implementation KW - modified multi-way Fiduccia-Mattheyses algorithm KW - cost estimation functions VL - 0 JA - VLSI Design, International Conference on ER -

M. Vootukuru, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

R. Vemuri, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

N. Kumar, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568066

In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail.

Index Terms:

logic partitioning, resource constrained RTL partitioning, multi-FPGA designs, register level designs, multiple FPGA implementation, modified multi-way Fiduccia-Mattheyses algorithm, cost estimation functions

Citation:

M. Vootukuru, R. Vemuri, N. Kumar, "Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs," vlsid, pp.140, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.