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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Allocation of FIFO Structures in RTL Data Paths
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
Heman Khanna, Cadence Design Systems (I) Pvt. Ltd.
M. Balakrishnan, I.I. T. Delhi, New Delhi 110016
Along with the functional units, storage and interconnects also contribute significantly to the data path cost. This paper addresses the issue of reducing the storage and interconnect cost by allocating queues for storing variables. In contrast to the earlier works, we support "regular" cdfgs and multi-cycle functional units for queue synthesis. Initial results on HLS benchmark examples have been encouraging and show the potential of data path cost reduction using queue synthesis. A novel feature of our work is the formulation of the problem for a variety of FIFO structures with their own ``queueing" criteria.
Citation:
Heman Khanna, M. Balakrishnan, "Allocation of FIFO Structures in RTL Data Paths," vlsid, pp.130, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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