We investigate the path delay fault testability of the adder function. A method to reduce the number of tests is presented and applied to several well-known hardware realizations, like the Carry Ripple Adder (CRA) and the Carry Look Ahead Adder (CLA). Depending on the structure we obtain linear or quasi-linear, i.e. O(n) or O(n\log n), respectively, size for a complete test of the whole adder with respect to its timing behavior, thus e.g. making feasible an on-line dynamic test for many adders currently in use.