9th International Conference on VLSI Design: VLSI in Mobile Communication
Improving accuracy in path delay fault coverage estimation
Bangalore, INDIA
January 03-January 06
ISBN: 0-8186-7228-5
K. Heragu, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
V.D. Agrawal, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
A recently published method computes path delay fault coverage from the count of the number of path faults newly sensitized by a simulated vector pair. Such an estimate is pessimistic since several paths may share a set of lines. In this paper, we present a continuum of approximate methods, approaching exact fault simulation, for a tradeoff between accuracy and complexity. Higher accuracy is obtained at the expense of CPU time. We propose the use of flags corresponding to fixed-length path-segments. A flag indicates whether or not the segment has been included in a previously detected path fault. A path fault detected by a pair of vectors is counted as a new detection only if it includes at least one segment not included in any previously covered path. This gives us a pessimistic estimate of the number of newly detected faults by a simulated vector pair. When the numbers of fan-in and fan-out branches per gate are small, the method adds a modest overhead to good machine simulation provided the flagged path-segments are short. As the length of segments is increased, the accuracy approaches that of exact fault simulation. Results show that the estimates with small segment lengths are very close to actual fault coverages.
Index Terms:
combinational circuits; fault diagnosis; logic testing; delays; circuit analysis computing; logic CAD; graph theory; path delay fault; fault coverage estimation; simulated vector pair; approximate methods; exact fault simulation; CPU time; fixed-length path-segments; fan-in branches; fan-out branches; flagged path-segments; segment lengths; combinational paths
Citation:
K. Heragu, J.H. Patel, V.D. Agrawal, "Improving accuracy in path delay fault coverage estimation," vlsid, pp.422, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996