In this paper, we present a novel method to eliminate logic hazards, in particular dynamic hazards, in asynchronous circuits synthesized from the signal transition graph (STG) specifications. The existing hazard removal techniques work with the logic implementation derived from the STG specifications. This paper describes algorithms to detect and eliminate dynamic hazards without implementing the logic. Our algorithms have the advantage of directly operating on the STG specifications. In order to implement logic, an STG needs to satisfy the complete state coding (CSC) property. We first review a relationship between the causal relations of the signal transitions and the resultant logic (two-level sum-of-products or product-of-sums) implementations. Using this relationship, we identify the causes of dynamic hazards and remove the hazards by adding appropriate internal signal transitions to the STG.