Self timed division and square-root extraction

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9th International Conference on VLSI Design: VLSI in Mobile Communication

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	A. Guyot, M. Renaudin, B. El Hassan, V. Levering, "Self timed division and square-root extraction," VLSI Design, International Conference on, pp. 376, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489638, author = {A. Guyot and M. Renaudin and B. El Hassan and V. Levering}, title = {Self timed division and square-root extraction}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {376}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489638}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Self timed division and square-root extraction SN - 1063-9667 SP EP A1 - A. Guyot, A1 - M. Renaudin, A1 - B. El Hassan, A1 - V. Levering, PY - 1996 KW - pipeline arithmetic; dividing circuits; integrated circuit design; iterative methods; self-timed integrated circuit; square-root extraction; mathematical algorithm; design methodology; functional blocks; logic level; quotient; binary notation; division; pipelined arithmetic VL - 0 JA - VLSI Design, International Conference on ER -

A. Guyot, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France

M. Renaudin, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France

B. El Hassan, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France

V. Levering, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489638

This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit implementing a simplified version of the algorithm is presented. The algorithm relies on two functional blocks, each simple enough to be fully detailed at the logic level in this paper. Besides its simplicity, the novelty of the algorithm lies in the fact that it delivers the quotient or the square root in conventional binary notation. The final remainder only has to be eventually converted.

Index Terms:

pipeline arithmetic; dividing circuits; integrated circuit design; iterative methods; self-timed integrated circuit; square-root extraction; mathematical algorithm; design methodology; functional blocks; logic level; quotient; binary notation; division; pipelined arithmetic

Citation:

A. Guyot, M. Renaudin, B. El Hassan, V. Levering, "Self timed division and square-root extraction," vlsid, pp.376, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

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