Low power realization of FIR filters using multirate architectures

V
VLSID
1996
9th International Conference on VLSI Design: VLSI in Mobile Communication
Abstract - Low power realization of FIR filters using multirate architectures

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	Similar Articles Articles by M. Mehendale Articles by S.D. Sherlekar Articles by G. Venkatesh

9th International Conference on VLSI Design: VLSI in Mobile Communication

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	M. Mehendale, S.D. Sherlekar, G. Venkatesh, "Low power realization of FIR filters using multirate architectures," VLSI Design, International Conference on, pp. 370, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489637, author = {M. Mehendale and S.D. Sherlekar and G. Venkatesh}, title = {Low power realization of FIR filters using multirate architectures}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {370}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489637}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Low power realization of FIR filters using multirate architectures SN - 1063-9667 SP EP A1 - M. Mehendale, A1 - S.D. Sherlekar, A1 - G. Venkatesh, PY - 1996 KW - FIR filters; digital filters; computational complexity; application specific integrated circuits; digital signal processing chips; low power realization; FIR filters; multirate architectures; computationally efficient implementations; computational complexity; power dissipation reduction; dedicated ASIC implementation; TMS320C2x/C5x programmable DSP; power analysis VL - 0 JA - VLSI Design, International Conference on ER -

M. Mehendale, Texas Instrum. (India) Ltd., Bangalore, India

S.D. Sherlekar, Texas Instrum. (India) Ltd., Bangalore, India

G. Venkatesh, Texas Instrum. (India) Ltd., Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489637

The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.

Index Terms:

FIR filters; digital filters; computational complexity; application specific integrated circuits; digital signal processing chips; low power realization; FIR filters; multirate architectures; computationally efficient implementations; computational complexity; power dissipation reduction; dedicated ASIC implementation; TMS320C2x/C5x programmable DSP; power analysis

Citation:

M. Mehendale, S.D. Sherlekar, G. Venkatesh, "Low power realization of FIR filters using multirate architectures," vlsid, pp.370, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

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