Dual rail static CMOS architecture for wave pipelining

V
VLSID
1996
9th International Conference on VLSI Design: VLSI in Mobile Communication
Abstract - Dual rail static CMOS architecture for wave pipelining

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	Similar Articles Articles by G. Enrique Fernandez Articles by R. Sridhar

9th International Conference on VLSI Design: VLSI in Mobile Communication

Dual rail static CMOS architecture for wave pipelining (PDF)

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	G. Enrique Fernandez, R. Sridhar, "Dual rail static CMOS architecture for wave pipelining," VLSI Design, International Conference on, pp. 335, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489628, author = {G. Enrique Fernandez and R. Sridhar}, title = {Dual rail static CMOS architecture for wave pipelining}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {335}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489628}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Dual rail static CMOS architecture for wave pipelining SN - 1063-9667 SP EP A1 - G. Enrique Fernandez, A1 - R. Sridhar, PY - 1996 KW - CMOS logic circuits; pipeline processing; capacitance; delays; combinational circuits; timing; dual rail static CMOS architecture; wave pipelining; digital systems; throughput; gate capacitance; storage elements; delay variations; DRSCMOS; multi-functional basic building blocks; power consumption; combinational logic block VL - 0 JA - VLSI Design, International Conference on ER -

G. Enrique Fernandez, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

R. Sridhar, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489628

Wave-pipelining is a special pipelining technique used in digital systems to achieve high throughput, with the use of gate capacitance as storage elements. An ideal system should have minimal delay variations amongst all paths. A dual-rail static CMOS (DRSCMOS) technique is presented for wave-pipelining. The availability of multi-functional basic building blocks and their low power consumption makes this an attractive approach.

Index Terms:

CMOS logic circuits; pipeline processing; capacitance; delays; combinational circuits; timing; dual rail static CMOS architecture; wave pipelining; digital systems; throughput; gate capacitance; storage elements; delay variations; DRSCMOS; multi-functional basic building blocks; power consumption; combinational logic block

Citation:

G. Enrique Fernandez, R. Sridhar, "Dual rail static CMOS architecture for wave pipelining," vlsid, pp.335, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

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