Challenges in Low Power Microprocessor Design

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Suresh Rajgopal

9th International Conference on VLSI Design: VLSI in Mobile Communication

Challenges in Low Power Microprocessor Design (PDF)

Bangalore, INDIA

January 03-January 06

ISBN: 0-8186-7228-5

	ASCII Text	x
	Suresh Rajgopal, "Challenges in Low Power Microprocessor Design," VLSI Design, International Conference on, pp. 329, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489625, author = {Suresh Rajgopal}, title = {Challenges in Low Power Microprocessor Design}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {329}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489625}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Challenges in Low Power Microprocessor Design SN - 1063-9667 SP EP A1 - Suresh Rajgopal, PY - 1996 KW - microprocessor design KW - low-power KW - power benchmarks KW - di/dt KW - clock gating KW - latch power KW - idle power KW - active power KW - clock enabling KW - max power KW - thermal power KW - transient power VL - 0 JA - VLSI Design, International Conference on ER -

Suresh Rajgopal, Microprocessor Technology Intel Corporation, Santa Clara

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489625

This paper addresses the challenge of controlling power dissipation in the microprocessor domain. Power efficiency in microprocessors is achieved not as much by by low watts, but more by increaed SpecInt/Watt. With process and voltage gains often being offset by increased frequency targets, reducing wasted power is becoming the theme in design. In this paper we address the challenges of performing low-power high-performance design. First we evaluate known low-power techniques, outlining design concerns and describing areas of maximum impact. Then we introduce the notion of benchmarks for power describing their relevance in system design as well as in power reduction.

Index Terms:

microprocessor design, low-power, power benchmarks, di/dt, clock gating, latch power, idle power, active power, clock enabling, max power, thermal power, transient power

Citation:

Suresh Rajgopal, "Challenges in Low Power Microprocessor Design," vlsid, pp.329, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.